1. Field of the Invention:
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a shallow-trench isolation (STI) structure in an integrated circuit.
2. Description of Related Art:
The shallow-trench isolation (STI) structure is a widely used isolation structure in integrated circuits for electrically isolating the various active components in the integrated circuit. A conventional method of forming an STI structure includes a first step of forming a trench in the substrate through an anisotropic etching process, a second step of depositing oxide into the trench, and a final step of performing a chemicalmechanical polishing (CMP) process to planarize the top surface of the oxide in the trench. The oxide in the trench then serves as the intended STI structure. One benefit of using the STI structure is that its topmost surface is substantially level with the topmost surface of the substrate.
One drawback to the foregoing method, however, is that the CMP process scratches the top surface of the oxide in the STI structure, thus forming undesired microscratches in the top surface of the oxide in the STI structure. The forming of these microscratches then causes some problems in the resulting IC device. To better depict this drawback, the conventional STI fabrication method is schematically depicted, step-by-step, in full detail in the following with reference to FIGs. 1A-1E.
Referring first to FIG. 1A, in the first step, a semiconductor substrate 100 is prepared. Subsequently, a pad oxide layer 102 is formed over the substrate 100 for surface protection of the substrate 100. After this, a mask layer 104 is formed over the pad oxide layer 102, preferably from silicon nitride through a low-pressure chemical vapor deposition (LPCVD) process.
Referring next to FIG. 1B, in the subsequent step, a selective etching process is performed to etch into a selected area of the wafer. Etching proceeds successively through the mask layer 104 and the pad oxide layer 102 until reaching a predefined depth in the substrate 100. Through this process, a trench 106 is formed in the substrate 100.
Referring next to FIG. 1C, in the subsequent step, a thermal oxidation process is performed on the wafer, whereby the exposed part of the substrate 100 is oxidized to form a liner oxide layer 108 on the bottom and sidewalls of the trench 106. This liner oxide layer 108 is formed to such an extent as to come into junction with the pad oxide layer 102. Next, a dielectric material, preferably silicon oxide, is deposited through an atmospheric-pressure chemical vapor deposition (APCVD) process into the trench 106 and also over the top surface of the wafer to thereby form an insulating layer 110. After this, a densification process is performed on the wafer in such a manner as to place the wafer in a gaseous nitrogen environment under a high temperature condition, whereby the insulating layer 110 is densified.
Referring next to FIG. 1D, in the subsequent step, a chemical-mechanical polishing (CMP) process is performed on the wafer until reaching the top surface of the mask layer 104, whereby all the surface part of the insulating layer 110 that is laid above the mask layer 104 is removed (the remaining part is here designated by the reference numeral 110a and is here and hereinafter referred to as an insulating plug). The CMP technique is a widely used and well-known surface polishing process in semiconductor fabrication, so details thereof will not be further described.
One drawback to the use of the CMP process, however, is that it scratches the top surface of the resulting insulating plug 110a, thus forming undesired microscratches 112 in the top surface of the insulating plug 110a. These microscratches 112 result because it is necessary to over-polish the mask layer 104 during the CMP process so as to ensure that the overlying part of the insulating layer 110 is entirely removed. Since the mask layer 104 (which is formed from silicon nitride) is harder than the insulating layer 110 (which is formed from silicon oxide), the slurry used in the CMP process together with the particles from the polished mask layer 104 abrade the top surface of the insulating plug 110a, thus resulting in formation of the microscratches 112 in the top surface of the insulating plug 110a.
Referring next to FIG. 1E, in the subsequent step, the mask layer 104 is entirely etched away by using a hot phosphate solution as the etchant. Next, the pad oxide layer 102 is also entirely etched away by using hydrofluoric acid (HF) as the etchant. Through these two etching processes, the insulating plug 110a (FIG. 1D) is also partly etched away (the remaining part thereof is here designated by the reference numeral 110b for distinguishing purpose). The remaining insulating plug 110b and the liner oxide layer 108 in the previously formed trench 106 (FIG. 1B) in combination constitute the intended STI structure.
One drawback to the use of the HF solution, however, is that it would also etch into the microscratches 112 in the top surface of the insulating plug 110a (FIG. 1D), thus further enlarging the microscratches 112. When conductive layers, such as doped polysilicon layers, are being formed on both sides of the insulating plug 110b, some of the doped polysilicon can be accidentally deposited into the microscratches 112, thus resulting in a bridging effect across the insulating plug 110b. The bridging effect across the insulating plug 110b causes leakage current to flow across the insulating plug 110b, thus making the resulting STI structure lose its isolating ability. As a consequence, the resulting IC device may be unreliable in operation. Moreover, it can cause pattern distortion that makes the resulting IC device inoperable, thus decreasing the yield rate of the wafer fabrication.